The present invention relates to a lead frame, and more particularly, to a multi-layer plated lead frame in which the structure of a plating layer is improved, such that a pre-plated frame (PPF) process is applied to a substrate made of an ferroalloy (Fe).
A semiconductor lead frame is an important element of a semiconductor package, together with the semiconductor chip. The lead frame connects the inside of the semiconductor package to the outside thereof, and supports the semiconductor chip. In general, such a semiconductor lead frame is manufactured by a stamping or etching method.
According to the stamping method, a thin plate material is formed into a predetermined shape using a press molding apparatus. Such a stamping method is mainly applied for mass producing lead frames.
Alternatively, the etching method is a chemical etching in which a predetermined portion of the material is eroded using a chemical, and this method is generally used to manufacture small quantities of lead frames.
A semiconductor lead frame manufactured by one of the above methods may include various structures according to the mounting type of lead frame on the substrate. FIG. 1 shows a general structure of the semiconductor lead frame.
In FIG. 1, the lead frame includes a die pad 11 for mounting and fixing a memory chip thereon, an inner lead 12 connected to the chip by wire bonding, and an outer lead 13 for connection with an external circuit.
The semiconductor lead frame having this structure forms a semiconductor package through assembly with other parts of the semiconductor, e.g., a memory chip.
In order to improve wire bonding between the semiconductor chip and the inner lead 12 of the lead frame, the die pad 11 and the inner lead 12 are plated with a metal. Also, in order to improve solderability, a solder plating is performed on a predetermined portion of the outer lead 13.
However, during the solder plating, a plating solution frequently encroaches on a region of the inner lead 12, so that an extra step of removing the unwanted plating solution is necessary.
To solve the problem, a pre-plated frame (PPF) method has been suggested. According to the pre-plated frame method, a material having excellent solder wettability is coated on a substrate prior to the semiconductor packaging process, to form a plating layer. Structures of the plating layer obtained by the above method are shown in FIGS. 2, 3 and 4.
Referring to FIG. 2, a nickel (Ni) plating layer 22, and a palladium (Pd) or Pd/Ni alloy plating layer 23, are sequentially formed on a copper (Cu) substrate 21, forming a multi-layer plating layer.
The lead frame of FIG. 3 includes a Ni plating layer 32, a Pd/Ni alloy plating layer 33, a Ni plating layer 34, and a Pd plating layer 35, wherein the plating layers 32, 33, 34 and 35 are sequentially formed on a Cu substrate 31.
According to the lead frame of FIG. 4, a Ni plating layer 42 and a Pd or gold (Au) plating layer 43, are sequentially formed on a Cu substrate 41. Also, a Pd/Ni alloy plating layer 44, a Pd or Au plating layer 43' and a Pd plating layer 45 are formed on the Pd or Au plating layer 43.
The lead frames of FIGS. 2 through 4 are manufactured according to a pre-plated frame process by using Cu or Cu alloy as the substrate material. It is difficult, however, to apply the pre-plated frame process used above for forming the lead frames of FIGS. 2 through 4 on a substrate made of Alloy 42. Here, Alloy 42 consists of Ni, Fe and minor amount of other elements, and is widely used as a lead frame substrate material. However, Alloy 42 is seriously corroded by the assembly process in salty atmosphere. This is due to galvanic corrosion caused by the great difference in electrochemical potential between Fe of the Alloy 42 and Pd of the plating layer.